1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device including a vertical transistor and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2008-295831, filed Nov. 19, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
There have been known vertical metal oxide semiconductor transistors which will hereinafter be referred to as vertical MOS transistor. Japanese Unexamined Patent Application, First Publication, No. 2005-012214 discloses a vertical nMOSFET which includes an n+-relaxed SiGe drain, an epitaxial p-relaxed SiGe body, an epitaxial n+-tensile stressed Si, and an epitaxial tensile stressed channel.
Japanese Unexamined Patent Application, First Publication, No. 11-214684 discloses a semiconductor device including a MOS transistor. The MOS transistor includes an n-diffusion wiring layer. The MOS transistor also includes an n+-silicon selective epitaxial layer as a source region over the n-diffusion wiring layer. The MOS transistor also includes a p−-silicon selective epitaxial layer as a channel region over the n-diffusion wiring layer. The MOS transistor also includes an n+-silicon selective epitaxial layer as a drain region over the n-diffusion wiring layer.